library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

Library UNISIM;
use UNISIM.vcomponents.all;

entity twoWireInterface is
  Port( I2C_Clk : inout std_logic;
        I2C_Data : inout std_logic;
        FPGA_Clk : in std_logic;
        Sync : in std_logic);
end twoWireInterface;

architecture beh of twoWireInterface is

  component twoWireMaster is
    Port(FPGA_Clk : in std_logic;
       I2C_DataToBus : out std_logic;
       I2C_DataFromBus : in std_logic;
       I2C_DataDir : out std_logic;
       I2C_ClkToBus : out std_logic;
       I2C_ClkFromBus : in std_logic;
       I2C_ClkDir : out std_logic;
       Sync : in std_logic);
  end component;

  signal dataFromBus,dataToBus,dataDir : std_logic:='1';
  signal clkFromBus, clkToBus, clkDir : std_logic:='1';
  
begin

	Data_IOBUF : IOBUF generic map (DRIVE=>12,IBUF_DELAY_VALUE=>"0",IFD_DELAY_VALUE=>"AUTO",IOSTANDARD=>"DEFAULT",SLEW=>"SLOW")
	port map (dataFromBus,I2C_Data,dataToBus,dataDir);
	Clock_IOBUF : IOBUF generic map (DRIVE=>12,IBUF_DELAY_VALUE=>"0",IFD_DELAY_VALUE=>"AUTO",IOSTANDARD=>"DEFAULT",SLEW=>"SLOW")
	port map (clkFromBus,I2C_Clk,clkToBus,clkDir); 
	
	I2C_Master : twoWireMaster port map(FPGA_Clk,dataToBus,dataFromBus,dataDir,clkToBus,clkFromBus,clkDir,Sync);
	
end beh;